This invention relates to memory modules, and more particularly to adjusting trace impedances on memory modules.
Personal computers (PCs) and other electronic systems often use memory modules such as dual-inline memory modules (DIMMs). Memory modules have memory chips such as dynamic-random-access memories (DRAMs) mounted on a small printed-circuit board (PCB) or other substrate. Contact pads along one edge of the substrate make electrical contact when the memory module is plugged into a socket such as on a PC motherboard.
As these electronic systems operate at higher and higher speeds, signals driven to the memory modules must also operate at higher frequencies. Faster high-current drivers can be used to more rapidly drive current to charge and discharge the capacitances on the inputs of DRAM chips on the memory modules. These DRAM-input capacitances can be significant, producing a large capacitive load on the inputs to the memory modules, especially when many DRAM chips are mounted on the same memory module.
Further compounding the input-capacitance problem is the use of expansion memory. A PC motherboard may contain several memory-module sockets such as 2 or 4. Initially, only one socket may be populated with a memory module, but later the end-user may insert additional memory modules into the unused memory-module sockets to expand the memory capacity.
FIG. 1 shows a signal trace on a typical memory module. Register 10 on a DIMM includes driver 12 that drives line 14. Line 14 is the address line A0, but could be other address or control lines generated by a memory controller on a PC motherboard.
Contact pads along an edge of DIMM 20 make electrical contact with metal tabs inside the memory module socket. Lines 14, 16 are wiring traces on or within the memory module board of DIMM 20.
DIMM 20 contains eight DRAM chips 21-28. Dram chips 21-28 can be synchronous DRAMs (SDRAMs) that receive a clock as one of the control lines. Some DIMM modules may have fewer or more DRAM chips than the 8 shown in this example.
The A0 address signal must be routed to inputs of all 8 DRAM chips 21-28. Line 14 is initially one trace, but then branches into two branches at junction A. One branch continues to junction B1, where it again splits, ultimately to four branches C1, C2, C3, C4 that connect to inputs of DRAM chips 21-24. The lower branch continues to junction B2, where it again splits, ultimately to four more branches C5, C6, C7, C8 that connect to inputs of DRAM chips 25-28.
FIG. 2 highlights a reflection problem caused by trace junctions. Line 14 has an impedance determined primarily by its width, thickness, and length, and proximity to other wiring traces and layers. Often minimum-width wiring traces are used for all signal traces on the memory module, although power and ground may use wider traces.
The input trace, line 14, using the minimum trace width, has a characteristic impedance of about 60 ohms. The branch from junction A to junction B1 also uses the minimum width, and also has an impedance of 60 ohms. The final stubs to the inputs of DRAM chips 21-28 are very short but usually have the same impedance, about 60 ohms.
When the output driver of the register drives the signal to the opposite state, the initial wave-front or surge of current i travels down line 14 toward junction A. At junction A, the current is split into two halves or roughly i/2 each. At junctions B1, B2, the current is again divided. Since wiring traces have the same impedance before and after junction A, the initial voltage from the initial wave-front traveling along the branch to B1 is half the voltage before junction A, since the voltage is=i*Z before junction A, and the voltage is=i/2*Z along each branch after junction A. If impedance Z before A and impedance Z after A are the same, then the voltage at the trace segment from A to B1 or B2 is one half of the voltage at A.
Of course, these are rough estimates, and actual impedances will not be exactly equal, and the voltage drop-off after junction A may not be exactly 50%. However, the general idea is that the instantaneous voltage of the initial wave-front drops off after junction A when the same-width and same-thickness wiring traces are used before and after the junction.
Further voltage reduction of that initial wave-front can occur at junctions B1, B2, and further reduce the initial voltage applied to the inputs to DRAM chips 21-28. Reflections can also occur at the junctions and from the chip inputs.
As higher frequencies are used, wiring traces act more like transmission lines. Reflections from junctions and chip inputs travel backward along the line after the initial wave-front reaches the junctions or chip inputs. These reflections disturb instantaneous voltages along the line, and take time to settle. This settling time can reduce the practical operating frequency.
Termination circuits such as resistors are normally added to trace endpoints on other systems, but memory modules are so small that such terminations are not desirable.
FIG. 3 is a timing diagram showing the problem of voltage drop-off at trace junctions on the memory module. The register output may drive signal A0 high in response to a rising edge of clock CK. After some delay from the clock, the driver drives an initial wave-front down the trace to the memory module. The voltage at the chip inputs C2, C3, . . . is shown. Voltage drop-offs at junctions A and B1 reduce the voltage of the initial wave-front, and cause reflections that reduce the voltage at C1, C2, such as knee 32 caused by junction A, and knee 34, caused by junction B1.
The delay until the voltage at DRAM inputs C2, C3 rises above the logic threshold is the propagation delay. This propagation delay is extended due to knee 32. The logic threshold of the DRAM input is not reached by the initial wave-front. Instead, the voltage rises above the logic threshold only after one or more reflection returns and then boost the voltage above the logic threshold.
The parent application disclosed a memory module with trace-impedance matching at trace junctions. FIG. 4 highlights the concept of impedance matching at a wiring-trace junction on a memory module. A register output signal, such as address A0 drives line 15. At junction A, input line 15 splits into two branches (lines 16) to secondary junctions B1, B2. Then the wiring traces split again to reach inputs C1-C8 of eight DRAM chips on the memory module.
The impedance mis-match at junction A is eliminated by adjusting the input impedance to match the output impedance. The impedance of input line 15 is adjusted to match the combination of the impedances of the two branches of lines 16. Lines 16 are typically minimum-width and minimum-thickness wiring traces on or within the memory module substrate and have a characteristic impedance of 60 ohms each. The combination of the two parallel 60-ohm impedances is 30 ohms (The equivalent impedance Z=1/[(1/Z1)+(1/Z2)] where Z1 and Z2 are in parallel). Thus input line 15 is adjusted to have a 30-ohm impedance. This can be done by doubling the width of the wiring trace for input line 15 relative to the width of lines 16.
By matching the input impedance of line 15 to the combined output impedance of the two lines 16, impedance mis-match at junction A can be avoided. This improves signal integrity.
A larger driver may be needed to drive the reduced impedance of input line 15. With the larger driver driving input line 15 with a reduced impedance of 30 ohms, the current delivered to junction A from input line 15 by the initial wave-front is double the current delivered in FIG. 2 by the 60-ohm line 14.
This initial current 2i into junction A is split into two branches of lines 16, each receiving current i, about half the current entering junction A. The initial current in each branch is again split at junctions B1 and B2 into currents of i/2. This is double the i/4 current delivered in FIG. 2.
The doubled current delivered to the DRAM inputs produces a higher initial voltage rise at the inputs C1-C8 of the DRAM chips. This higher initial voltage rise can be above the logic threshold (such as 1.2 volts, or Vcc/2, or another intermediate value), allowing the switching point voltage to be reached on the initial wave-front before any knees due to reflections occur. Then the propagation time is not delayed due to settling time for reflections and ringing. The first reflection from junction A is eliminated when the impedance matching is exact, or reduced significantly even when the input and output impedances are not precisely matched.
The actual impedances of lines 16 may not be 60 ohm, but may be some other value. Likewise, input line 15 may not be exactly 30-ohm impedance, and there may be some impedance mis-match even when input line 15 is double the width of output lines 16, such as a mis-match of 10% or even 20%. However, the concepts of impedance matching at wiring junctions are best illustrated with this simplified example.
The length of each branch of lines 16 is 2.15 inches in one embodiment, and the length of the distribution lines after point B1, and after point B2, is about half, at 1 inch or so. Significant reflections can occur at junctions A and B1, B2.
The lengths of final stubs from the line after point B1 to DRAM inputs C1, C2 . . . C4 and from the line after point B2 to DRAM inputs C5, C6 . . . C8 are only 0.25 inch or so. Thus the reflections caused by the final stubs to the DRAM inputs is much less than the reflections caused by junctions A, B1, and B2.
Some memory modules have DRAM chips mounted in pairs on opposite surfaces of the module board. Other modules stack DRAM chips on top of each other in a piggy-back fashion. It is desirable to extend the trace-matching taught in the parent application to these memory modules with paired DRAMs. Other memory modules may have varying numbers of DRAM chips, and may have multi-way trace junctions, such as 3-way or 4-way junctions. It is desirous to extend the principals of impedance matching at junctions to various trace topologies.
Some DRAM's have differential inputs rather than single-ended inputs. For example, a clock may be differential, having two signal inputs to each DRAM chip. A terminating resistor may be placed between the two signal inputs to terminate the differential signals. However, this termination is undesirable. It is further desired to extend trace impedance-matching to differential signals. For these differential signals, it is desired to reach the differential cross-over point on the initial wave-front to reduce delays due to transmission-line effects.